搜索资源列表
Multi_SI
- 用verilog实现的乘法器，可以综合，经过验证。-Implementation multiplication with verilog.
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
mux16
- 基于FPGA的verilog编写的乘法器-FPGA-based multiplier verilog prepared
Multiplier-digital-tube-display
- 乘法器数码管显示，FPGA的verilog代码-Multiplier digital tube display
multiply_verilog
- 几个常用的乘法器的verilog实现，包括普通乘法器，时序乘法器，行波乘法器-Several commonly used multiplier verilog achieve, including ordinary multiplier, multiplier timing, traveling wave multiplier, etc.
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
booth-mutiplier
- booth乘法器的verilog实现及仿真。 内含verilog源码和modelisim仿真源码，清晰的实现了硬件乘法器，代码注释清晰-booth multiplier verilog verilog implementation and simulation contains the source code and modelisim simulation code, clear notes
Multiply8-6
- FPGA verilog用移位相加的方式来实现8位的乘法器-FPGA verilog With shift and add a way to achieve 8 multiplier
ParallelSerialMult
- 用verilog代码实现了 并行线性序列乘法器，流水线技术实现了乘法操作-Verilog code using a linear sequence of parallel multipliers, pipeline technology to achieve a multiplication operation
multiplier.v
- 依旧是自己写的一个8*8的乘法器的verilog代码，所以请大家下载，-Verilog still write their own code of an 8* 8 multiplier, so please download, thank you
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
multiplying-unit
- fpga verilog入门经典系列完整版，下载即用:乘法器-fpga verilog multiply
mul16
- 16位二进制数移位乘法器的实现,使用Verilog HDL实现-The realization of the 16 bit binary number shifting multiplier, use Verilog HDL to implement
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
4booth_multiplie_module_2
- 采用Verilog对Booth算法乘法器的改进，对想学习乘法器的会有很大的帮助。-Improved algorithm using Verilog Booth multiplier, multiplier want to learn to have a lot of help.
5lut_multiplier_module
- 利用Verilog编写的基于Quartersquare的查表法乘法器，对想学习乘法器的将会有很大的帮助-Use Verilog prepared Quartersquare the look-up table based multiplier multiplier will want to learn a great help
6modified_booth_multiplier_module
- 利用Verilog编写的ModifiedBooth乘法器，对想学习乘法器的将会有很大的帮助-Use Verilog prepared ModifiedBooth multiplier, multiplier will want to learn a great help
mul
- 使用Verilog实现的原码4位数的移位乘法器-Using Verilog to realize the original code 4 bit shift multiplier
ad5544
- 模数乘法器AD5544的Verilog源程序，已在项目中验证了其可行。-Verilog source AD5544 analog multiplier, and have verified its feasibility in the project.
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat